1. Field
An embodiment of the present invention relates to the field of clock signal distribution and more particularly, to correcting a clock duty cycle.
2. Discussion of Related Art
Clock distribution networks are typically used to distribute a clock signal from a phase locked loop (PLL) circuit or other clock generation circuitry, for example, to various points across an integrated circuit chip, such as a microprocessor.
The output clock signal provided by the PLL has a given duty cycle. It is typically desirable to match that duty cycle as closely as possible at the various end points of the clock distribution network across the integrated circuit chip. Additionally, it is desirable to be able to control the duty cycle of the clock signals at the receiving endpoints of the clock distribution network such that operation of the integrated circuit can be as predictable as possible. This is particularly important for high frequency integrated circuits.
Matching the duty cycles of clock signals across a clock distribution network, however, may not be straightforward. As a clock signal is distributed across an integrated circuit chip, its duty cycle tends to get distorted due to variations in temperature, voltage, supply noise and other factors in the distribution path. These variations make it difficult to ensure a particular duty cycle for clock signals at the various receiving points of a clock distribution network. This inability to ensure desired clock signal duty cycles across a clock distribution network may result in a need to provide wider operating margins and thus, compromise potential performance of an integrated circuit chip.